We build AI-assisted engineering, simulation, and technical systems for modern electronics development — from circuit design and SPICE-grade analysis to embedded systems, automation, and next-generation engineering workflows.
Five practice areas, one unified workflow. We treat simulation, behavioural modelling, machine learning, AI tooling, and firmware as a single design surface — so the analog reality and the software model stay in sync.
Mixed-signal modelling — analog front-ends and digital control in one netlist. Transient, AC and Monte-Carlo tolerance runs on our in-house simulator, with parasitics back-annotated from layout. Every model is correlated against bench measurements before it informs a board.
Device and subsystem models distilled from datasheets and bench data — fast enough for system-level sweeps, yet matched to silicon. The model stays the contract between the analog reality and the firmware above it.
Quantisation-aware training, INT8/INT4 deployment, on-device sensor fusion. Models that fit in 256 kB and still beat the threshold-based heuristic they replace.
Internal copilots that read your netlists, datasheets, and test logs. Closed-loop assistants that propose component choices, flag tolerance violations, and write test fixtures.
Production firmware in Rust and C. RTOS bring-up, bootloaders, secure OTA, deterministic schedulers. We ship the version that survives field deployment — not the demo.
Every project ships with a virtual twin. We co-simulate the analog front-end, the MCU, and the ML pipeline so that what you see in the lab is what you get in the field. Below: a low-pass RC stage swept from DC to 1 MHz — magnitude in dB, phase in degrees, updated each frame.
A human writes the intent — spec, constraints, targets. Plain requirements, not a finished schematic.
The model proposes a candidate: topology, values, a netlist — drawn from the part libraries we already trust.
Our simulator runs it — transient, AC, corners, tolerances. Pass or fail measured against the spec, not opinion.
It reads why a measurement failed, revises the design, and hands it straight back to the simulator.
Triaxial accelerometer on the drive housing, sampled at 25.6 kHz, with the FFT and a quantised 3-class CNN (healthy / watch / fault) running int8 on an STM32H7 — no cloud link, inference under 40 ms. Trained on seeded-fault data from a bench rig, then tuned on the line. Over the first 90 days: 23 % fewer unscheduled stops, at a false-alarm rate the maintenance team signed off on.
Instrumentation front-end with DC servo and right-leg drive into a 24-bit delta-sigma ADC, input-referred noise held under 0.4 µVrms across the ECG band. The analog path was modelled in SPICE and co-simulated against the MCU firmware before layout, so bring-up matched the model on the first board. 92 % first-spin yield on the pilot batch; full noise and CMRR characterisation handed over with the boards.
A retrieval pipeline over the group's netlists, datasheets and regression logs, with tool calls for parametric part search. It proposes alternates that stay inside tolerance and derating, drafts first-pass test plans, and cites the source for every claim — an engineer still signs off. Runs entirely on internal infrastructure; across ~40 reviews it cut review time by roughly 31 %, mostly by removing datasheet hunting.